Error-Corrected Memory and Logic on a Heavy-Hex Superconducting-Qubit Processor

The first text appears to be an excerpt from a research paper detailing experimental results, while the second text is a bibliography/reference list for a paper titled Error-Corrected Memory and Logic on a Heavy-Hex Superconducting-Qubit Processor.

I will now synthesize these into one comprehensive, detailed summary of the research described in the first text, contextualized by the references provided.

Comprehensive Research Summary: Defect Mitigation and Noise-Informed Error Correction in Large Monolithic Superconducting Quantum Processors

This research details advanced strategies implemented to maintain high-fidelity quantum computation on a large, monolithic array of 156 superconducting qubits arranged in a heavy-hexagonal lattice. The core challenge addressed is the presence of underperforming components (defects) and leakage errors, which severely limit the performance ceiling of current error correction schemes. The authors demonstrate that by integrating defect exclusion techniques with noise-informed decoding and post-selection filters, significant improvements in logical error probabilities can be achieved across both quantum memory experiments and measurement-based logic operations.

Key Findings and Strategies Implemented

1. Defect Exclusion for Code Performance:

The central theme of the work is overcoming performance bottlenecks caused by defects. The authors introduce defect exclusion techniques specifically tailored for the dynamic compass code implemented on this processor. They identify specific underperforming qubits and couplers—notably around qubits 85, 146, and 46—which exhibited significantly larger error rates (2-3 orders of magnitude higher than the median) in CZ gates. By strategically excluding these defective components from the active code patch (e.g., placing a 7 times 7 code to avoid the bottom row entirely), they demonstrate that performance can be maintained even when working on monolithic processors containing underperforming elements. The authors note that increasing qubit connectivity can enhance tolerance to defects, suggesting future designs should prioritize this aspect.

2. Enhanced Error Correction Metrics:

The application of these combined strategies yields substantial quantitative improvements:

• Memory Experiments: When combining ACES-informed BeliefMatching decoding, defect mitigation, and leakage post-selection in full-device memory experiments, the logical error probabilities per round were reduced to 4.11% (Z basis) and 2.56% (X basis). This represents a 32.3% and 35.2% improvement over the baseline performance, respectively, when compared to results without any post-selection or defect mitigation (which yielded 4.4% and 2.9%).

• Stability Experiments: The use of defect exclusion combined with noise-informed decoding allows for continual error suppression up to 30 rounds of syndrome extraction. Without defect mitigation, performance plateaus around round 12. At the 30-round mark, this technique provides an overall 56% improvement in failure probability.

3. Leakage Error Mitigation:

The research highlights the critical role of leakage errors. The authors investigate this by performing post-selection on runs without any detected leakage. This post-selection consistently improves the performance of logical elements. Furthermore, they observe that good noise characterization and accurate decoding are insufficient on their own; however, combining them with defect exclusion and leakage post-selection produces clear error suppression up to N=30 rounds.

4. High-Fidelity Logic Operations (Lattice Surgery):

For implementing fault-tolerant logic via lattice surgery, the authors show powerful synergistic effects from filtering techniques:

• Using only pre-selection filters yields lower bounds on Bell fidelities of 77.3%.

• When combining pre-selection filters with logical gap post-selection, the Bell fidelity is boosted to above 97.6%, with a post-selection yield of 27%. This combination is qualitatively different from simple post-selection and allows for probing the failure mechanisms associated directly with the logic gate itself, rather than initialization or preparation errors.

Context and Future Directions

The paper places its findings within the broader context of developing fault-tolerant quantum hardware, referencing established techniques such as surface codes (implied by references [90], [102]) and various decoding methods (e.g., BeliefMatching [83], Neural Network Decoders [97], Tesseract search-based decoders [99]).

Key Takeaways for Future Hardware:

The authors conclude that the primary bottleneck for scaling up performance is component homogeneity and fidelity. They strongly suggest that future generations of quantum processors must focus on:

1. Improving Component Homogeneity: Reducing the need for excessive defect exclusion by manufacturing chips with better uniformity.

2. Active Leakage Removal: Implementing fast, multilevel reset techniques to actively mitigate leakage errors during operation.

3. Connectivity: Considering designs with greater qubit connectivity to inherently increase tolerance to fabrication defects and reduce the reliance on complex exclusion strategies that reduce code distance.

In summary, this work provides a robust framework demonstrating that for large-scale superconducting processors, the most effective path to high-fidelity fault tolerance involves a multi-pronged approach: (1) Noise-informed decoding, (2) Targeted defect exclusion based on component characterization, and (3) Post-selection filters specifically designed to suppress leakage errors.

1. Bold header: Defect-Mitigation in Dynamic Codes

This capability allows an AI system to operate a large dynamic compass code on an array of 156 superconducting qubits by implementing strategies to exclude underperforming components, resulting in improvements of up to 35% in logical error probabilities for a memory experiment.

2. Bold header: Noise-Informed Decoding with ACES Data

The AI system can utilize noise-informed decoder combined with strategies to exclude the worst-performing qubits and couplers, specifically using ACES noise information to obtain more accurate characterization of the system during syndrome extraction, leading to performance gains.

3. Bold header: Leakage Post-Selection for Stability

The AI system can employ post-selecting on shots with a low probability of leakage errors and use leakage pre-selection, which results in substantial improvements from removing shots that prepared an initial code state with error.

4. Bold header: Fault-Tolerant Logic via Lattice Surgery

The AI system can perform fault-tolerant logic through lattice surgery, achieving Bell fidelities above 97% when combining techniques like pre-selection filters and logical gap post-selection using exclusive decoding increases these fidelities to above 97%.

5. Bold header: Adaptive Code Distance Management

The system can dynamically adjust the code structure, as demonstrated by the dynamic compass code which allows for all stabilizers to remain low weight, even when excluding defects, resulting in a Z-distance of the code which is lowered by 2 while maintaining X-distance.

Large quantum computations require high-fidelity error-corrected memory and fault-tolerant logical operations. To achieve these with superconducting circuits, quantum processors will need many components operating with low error rates. In practice, fabrication of monolithic superconducting devices produces unavoidable heterogeneity in component performance, which the quantum computer must accommodate. We implement strategies to operate a large dynamic compass code on an array of 156 superconducting qubits arranged on a heavy-hexagonal lattice, making use of the entire monolithic quantum processor and redesigning our measurement schedule to exclude underperforming components. We demonstrate improvements of up to 35% in logical error probabilities for a memory experiment by using a noise-informed decoder combined with strategies to exclude the worst-performing qubits and couplers, along with post-selecting on shots with a low probability of leakage errors. In addition to these memory results, we also observe performance gains of up to 56% when these strategies are applied to measurement-based logic, demonstrated by stability experiments. We furthermore demonstrate high-fidelity fault-tolerant logic through lattice surgery. Through pre-selection filtering techniques, we can obtain Bell fidelities above 77%, and further logical gap post-selection using exclusive decoding increases these fidelities to above 97%. Our experiments demonstrate that high performance can be maintained in key elements of fault-tolerant quantum memory and logic when working on monolithic superconducting quantum processors with underperforming components, by using a suite of noise-informed quantum error correction strategies.