A Survey on LLM-Integrated Hardware Design Verification

arXiv:2610.10580 · cs.AR, cs.AI, cs.SE · Submitted 2026-10-06 · Read on arXiv

cs.AR, cs.AI, cs.SE

Submitted: 2026-10-06

Updated: 2026-10-06

Terminology

Verification — 1× in this paper · explained in 2 episodes

Sources

VerilogReader: LLM-Aided Hardware Test Generation
Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog
AI-Assisted Hardware Security Verification: A Survey and AI Accelerator Case Study
AutoGen: Enabling Next-Gen LLM Applications via Multi-Agent Conversation
HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs
UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification
FuzzWiz -- Fuzzing Framework for Efficient Hardware Coverage
LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines
LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation
Spec2Cov: An Agentic Framework for Code Coverage Closure of Digital Hardware Designs
PRO-V-R1: Reasoning Enhanced Programming Agent for RTL Verification
UCAgent: An End-to-End Agent for Block-Level Functional Verification
From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification
A Multi-Agent Generative AI Framework for IC Module-Level Verification Automation
SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models
TB or Not TB: Coverage-Driven Direct Preference Optimization for Verilog Stimulus Generation
LLM4Cov: Execution-Aware Agentic Learning for High-coverage Testbench Generation
Structured Testbench Generation for LLM-Driven HDL Design and Verification-Oriented Data Curation
Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
AssertFix: Empowering Automated Assertion Fix via Large Language Models

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