CircuitGate: Logic-Consistent Circuit-Level Functional Modeling for And-Inverter Graphs

arXiv:2610.09549 · cs.LG · Submitted 2026-10-07 · Read on arXiv

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Introduction to the show: ident: AI Radio. Generated commentary on the latest Artificial Intelligence papers.

Tom: I'm Tom.

Jane: And I'm Jane, here with Lu, Meng and our in-house large language model, Lalam.

Tom: Today's paper: "CircuitGate: Logic-Consistent Circuit-Level Functional Modeling for And-Inverter Graphs".

Jane: The gist CircuitGate proposes a function-aware representation learning framework for And-Inverter Graphs that advances from gate-level semantics to circuit-level functional modeling by explicitly encoding global primary-input support and modeling support-overlapaware…

Tom: First, who's behind it and why it matters.

Paper summary: Tom: So to wrap up the "CircuitGate: Logic-Consistent Circuit-Level Functional Modeling for And-Inverter Graphs" paper, what did we actually learn about its main contribution?

Jane: The paper proposes a framework that advances AIG representation learning by explicitly encoding global primary-input support and modeling support-overlap aware reconvergence to achieve circuit-level functional modeling.

Lu: It moves the field from gate-level semantics to circuit-level functional modeling by jointly capturing global PI dependencies and reconvergent fanin relationships through context augmentation, global dependency encoding, and dependency learning.

Meng: From an engineering standpoint, the main thing is that this approach yields the lowest MAE on both equivalent-gate identification and signal-probability prediction while keeping inference latency competitive.

Lalam: The authors demonstrate this by reducing MAE over the second-best methods by twenty-one point seven percent and thirteen point eight percent on ForgeEDA for equivalent-gate identification and signal-probability prediction, respectively.

Tom: It really highlights the value of circuit-level functional priors when building accurate and efficient AIG representations because it's not just about local structure anymore.

Jane: And this work systematically analyzes existing methods to identify that fundamental gap between gate-level semantic modeling and true circuit-level functional representation, showing that global dependencies matter.

Lu: It suggests that future work should focus on how these global PI dependencies can be generalized beyond And-Inverter Graphs to other types of complex digital systems.

Meng: For me, the main implication is that if we want robust AI models for hardware verification or synthesis, we need to incorporate these kinds of circuit-level functional priors directly into the representation learning process.

Conclusion: Tom: So we’ve been looking at CircuitGate, and now we’re getting to the end of this thing.

Jane: It seems like they’ve taken something that was focused on individual gates and tried to figure out how those little pieces fit together into a whole circuit function.

Tom: Exactly. The title itself, "Logic-Consistent Circuit-Level Functional Modeling," suggests they went beyond just looking at the wires and started modeling the actual behavior of the whole circuit.

Lu: Yeah, it’s about moving from local structure to global function by explicitly handling those primary inputs across the entire system.

Meng: From a deployment view, that means we're not just looking at one gate in isolation; we're getting a representation that should be consistent whether we synthesize the circuit in ten different ways.

Lalam: The authors showed they achieved this by combining global primary input dependencies with reconvergent fanin modeling, which is pretty clever for handling those shared parts of the circuit.

Jane: So, what does this actually mean when we look at it? If you're building an AI model for hardware verification or synthesis, how does this framework fit in?

Tom: It means that instead of just relying on local patterns that might change with minor structural tweaks, you get a representation that respects the underlying functional rules of the circuit.

Lu: The paper shows they can reduce the mean absolute error by about twenty-two percent on a big benchmark, which is significant for how accurate those representations are.

Meng: Twenty-two percent reduction is something we need to see when we’re talking about models that need to be deployed reliably, not just on perfect test cases.

Jane: It seems like the main implication here is that for complex digital systems, understanding the global support structure of inputs is more important than just looking at adjacent gates.

Tom: Right. The authors really showed how crucial those specific mechanisms—the PI-support encoding and that reconvergence descriptor—are for getting good results on the ForgeEDA benchmark.

Lu: And the ablation studies confirm that taking out either the primary input encoding or the reconvergence modeling causes a big drop in performance, which proves those components are doing important work.

Jane: So, if you're listening and you've been working on complex circuit representations, this paper suggests that focusing on those global dependencies is where the real gains are hiding.

Qifan Zhang, Ruijie Li, Fangzhou Zhang, Qian Ma, Hui Li, Furui Zhan, Yongpeng Wang, Liying Hao, Shikai Guo

Dalian Maritime University · The Hong Kong University of Science and Technology (Guangzhou)

cs.LG

Submitted: 2026-10-07

Updated: 2026-10-07

Comments: 16 pages, 3 figures, 11 tables. Qifan Zhang and Ruijie Li contributed equally. Qian Ma is the corresponding author

License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/

Importance score: 92/100

The gist: The gist CircuitGate proposes a function-aware representation learning framework for And-Inverter Graphs that advances from gate-level semantics to circuit-level functional modeling by explicitly

Key concepts

And-Inverter Graphs (AIGs): These are structured representations of digital circuits used for machine learning. They capture not just how individual gates connect locally, but also the functional dependencies across the entire circuit, which is crucial for understanding what a circuit actually computes.
Global PI-Dependency Encoding: This technique compresses complex information about all primary inputs influencing a gate into a fixed-size summary. It looks beyond immediate neighbors to capture global functional relationships, ensuring the model understands how distant parts of the circuit's inputs affect a specific output.
Reconvergent-Fanin Dependency Modeling: This focuses on gates where multiple signals converge from shared sources (reconvergent fanins). The framework models these shared support relationships using overlap information. This helps the model adaptively adjust how it processes input dependencies when those shared inputs are involved.
Logic-Inspired Constraints: These are mathematical rules derived from Boolean logic, such as ensuring that if an AND gate has certain input probabilities, the output probability must adhere to specific bounds. These constraints regularize the learning process to ensure the learned representations respect fundamental circuit behavior.

Summary

The gist CircuitGate proposes a function-aware representation learning framework for And-Inverter Graphs that advances from gate-level semantics to circuit-level functional modeling by explicitly encoding global primary-input support and modeling support-overlapaware reconvergence between fanins, which improves representation consistency under functionality-preserving transformations.

Motivation and Problem Statement

And-Inverter Graphs (AIGs) require models to capture functional dependencies beyond local structure and remain robust to functionality-preserving transformations As structured representations of complex digital systems, AIGs require models to capture functional dependencies beyond local structure and remain robust to functionality-preserving transformations. Existing approaches are predominantly based on GNNs and rely on local gate-level message passing, limiting their ability to capture circuit-level functional context and making the learned representations sensitive to topology-specific patterns. This limitation manifests in two key aspects: existing methods provide an incomplete characterization of circuit-level functional dependencies because local message passing is effective for modeling Boolean operations among neighboring gates, but the functionality of a circuit node is ultimately determined by the complete set of primary inputs (PIs) that influence its output. Second, existing methods exhibit limited consistency under functionality-preserving synthesis transformations because topology-driven representation models may encode implementation-specific structural patterns rather than intrinsic functional properties. This highlights the central challenge of how can we learn AIG representations that capture complete circuit-level functional dependencies beyond local topology while remaining consistent under functionality-preserving synthesis transformations.

CircuitGate Framework Components

CircuitGate is a unified framework consisting of three architectural components designed to augment local message passing with complementary sources of functional context.

Circuit-Level Context Augmentation incorporates EDA-native circuit-role information, including logic levels, fanout, output status, and PI-support coverage to enrich gate-level representations with circuit-level contextual priors. The EDA-native context vector is defined as xv = ov xeda v (1).
Global PI-Dependency Encoding explicitly encodes polarity-aware PI dependencies and compresses variable-size support sets into fixed-width representations to capture global functional dependencies beyond finite-hop message passing. This involves constructing parity-indexed structural PI-support sets Sq(v) = [u∈N0(v) Sq(u) ∪ [u∈N1(v) Sq⊕1(u)] (2), and summarizing them into a sketch sq(v) = P p∈Sq(v) tp p max(Sq(v), 1), (3).
Reconvergent-Fanin Dependency Modeling identifies shared-support relationships among reconvergent fanins and uses support-overlap-aware gating to adaptively modulate the contribution of PI-dependency context during node updates. This is characterized by a six-dimensional reconvergence descriptor nv, which encodes reconvergence presence, Jaccard support overlap, and other structural and polarity-related properties.

Training Objective and Logic Constraints

To improve representation consistency under synthesis-induced topology changes, CircuitGate augments task supervision with logic-inspired regularization. The complete training objective is Ltrain = Ltask + λlogic λNOTLNOT + λANDLAND (11).

((i) Task Supervision)

The task supervision involves predicting pv = σ(fp(tanh(Wzh(L)v))), where the two supervised losses are Lprob = 1/V X v∈V pv − yv, Leq = 1/Q X (i,j)∈Q sij − yeq ij, and Ltask = Leq + αLprob (13).

((ii) Logic-Inspired Constraints)

Logic-inspired constraints are incorporated to regularize local Boolean semantics, penalizing violations of NOT complementarity and AND probability bounds through LNOT and LAND terms. For an AND input relation (u, o), the Frechet bounds are defined as p o = [peao + pebo − 1]+, po = min(peao, pebo) (9).

Experimental Results and Contributions

CircuitGate was evaluated on the ForgeEDA benchmark and further validated on EPFL and ITC’99 benchmarks. Across equivalent-gate identification, CircuitGate consistently outperforms existing methods, achieving up to 21.7% and 14.2% reductions in MAE. Under direct ForgeEDA-to-OpenABC transfer without fine-tuning, CircuitGate also achieves the best equivalent-gate identification performance, demonstrating strong cross-dataset generalization. The main contributions of this work are:

((i) Systematic Analysis)

We provide a systematic analysis of existing AIG representation learning methods and identify a fundamental gap between gate-level semantic modeling and circuit-level functional representation, specifically that current approaches lack effective mechanisms for capturing global functional dependencies.

((ii) Proposed Framework)

We propose CircuitGate, a unified framework that advances AIG representation learning from local topology-driven modeling toward circuit-level functional dependency modeling by jointly capturing global PI dependencies and support-overlap-aware reconvergence through circuit-level context modeling, global dependency encoding, and reconvergent-fanin dependency learning.

((iii) Performance)

We primarily evaluate CircuitGate on the large-scale ForgeEDA industrial EDA benchmark and demonstrate that it reduces MAE over the second-best methods by 21.7% and 13.8% on ForgeEDA for equivalent-gate identification and signal-probability prediction, respectively.

Scalability and Robustness

CircuitGate maintains practical preprocessing costs on large-scale complete circuits, with the largest evaluated graph containing 525,762 nodes requiring 14.03 s of mandatory feature construction. Furthermore, CircuitGate achieves the highest CKA under all four synthesis transformations, with an average CKA of 0.8341. These results indicate that CircuitGate learns more consistent representations under functionality-preserving topology variations. The ablation studies further highlight the importance of global PI dependencies and reconvergent-fanin relationships, showing that removing PI-support encoding causes the largest MAE degradation on ForgeEDA (34.4%).

Conclusion

CircuitGate achieves the lowest MAE on both equivalent-gate identification and signal-probability prediction while maintaining competitive inference latency. The ablation results further highlight the contributions of PI-support encoding and reconvergence modeling, supporting the value of circuit-level functional priors for accurate and efficient AIG representation learning.

The paper is available at https://anonymous.4open.science/r/CircuitGate/.

Improvements for AI systems

The improved system can learn circuit-level functional dependencies beyond local topology by explicitly modeling global primary-input (PI) support and support-overlap-aware reconvergence between fanins, as described in Section 2.
The system gains robustness to synthesis transformations because it augments topology-driven message passing with complementary contexts and incorporates logic-inspired Boolean constraints to encourage functionally consistent representations, addressing the challenge: How can we learn AIG representations that capture complete circuit-level functional dependencies beyond local topology while remaining consistent under functionality-preserving synthesis transformations?
The system achieves superior equivalent-gate identification by encoding global dependencies via fixed-width sketches, as detailed in Section 3.3, allowing it to distinguish between locally similar nodes with different global dependencies.
The system enhances signal-probability prediction accuracy by leveraging circuit-level context, which includes logic levels, fanout, output status, and PI-support coverage, providing a richer input for node updates as defined in Section 3.2.
The system maintains high representation consistency under structural changes by using the CKA metric to measure consistency between representations before and after synthesis transformations, achieving the highest CKA under all four synthesis transformations (Table 5).