VHDL-REPOBENCH: A Repository-Level Benchmark for Evaluating Large Language Models on VHDL Design Generation
cs.PL, cs.AR, cs.CL
Submitted: 2026-10-04
Updated: 2026-10-04
Terminology
Sources
- RTL++: Graph-enhanced LLM for RTL Code Generation
- CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarization
- SysVCoder: An LLM-Driven Framework for Systematic Generation of System-Level Design
- Qwen Technical Report
- Code Llama: Open Foundation Models for Code
- Evaluating Large Language Models Trained on Code
- RepoCoder: Repository-Level Code Completion Through Iterative Retrieval and Generation
- VHDL-Eval: A Framework for Evaluating Large Language Models in VHDL Code Generation
- Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
- DeepSeek-V3 Technical Report
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