Trinity: One Differentiable Physics for Training, Refining and Scoring Generative Floorplanners
cs.LG, cs.AR
Submitted: 2026-10-04
Updated: 2026-10-04
Comments: Shih-Ying Yeh and Tzu-Sian Wang contributed equally. 85 pages, 65 figures, 67 tables. Project page: https://kohaku-lab.github.io/Trinity/ Code: https://github.com/Kohaku-Lab/Trinity Models: https://huggingface.co/KBlueLeaf/Trinity
Code: https://github.com/Kohaku-Lab/Trinity
Project page: https://kohaku-lab.github.io/Trinity
License: http://creativecommons.org/licenses/by/4.0/
The gist: Floorplanning arranges the blocks of a chip and decides their shapes under objectives that press blocks together, short wirelength and a small outline, and constraints that hold them apart,
Abstract
Floorplanning arranges the blocks of a chip and decides their shapes under objectives that press blocks together, short wirelength and a small outline, and constraints that hold them apart, non-overlap, clusters, MIB shapes and boundary blocks. Recent diffusion placers train on reference layouts alone and leave this coupled system to guidance, post-hoc loops and a legalizer, reporting only the endpoint, which hides what the generator contributes. We re-implement four of them under one recipe on FloorSet, score raw, refined and legalized layouts on one scale, and propose Trinity, a flow-matching floorplanner whose six differentiable functions for the constraints and objectives are its training loss term, the energy of a closed-form refiner after sampling and the base of a soft cost for every stage. The network thus learns the correction prior placers apply in their samplers, and sampling needs no guidance. Stage by stage, the training term lowers a plain transformer's raw soft cost by 26% and matters most at short budgets, the shared refiner decides more of the final cost than the generator and matches a ported placer's loop in 16 to 660 times fewer steps, Trinity's refined soft cost is 36% below the best ported pipeline, the soft cost ranks settings as the contest's hard cost does, and on the FloorSet val set the pipeline reaches a mean hard cost of 1.014 in 1.63 s per case.
Sources
- CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA)
- A Generalization of Transformer Networks to Graphs
- PARSAC: Fast, Human-quality Floorplanning for Modern SoCs with Complex Design Constraints
- Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms
- FlowPlace: Flow Matching for Chip Placement
- BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement
- Physics-Guided Geometric Diffusion for Macro Placement Generation
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