An Executable Benchmark for LLM-Based HLS Repair:Design Complexity and Repair Underconstraint
cs.AR, cs.AI
Submitted: 2026-10-02
Updated: 2026-10-02
License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
Terminology
Sources
- ARSP: Automated Repair of Verilog Designs via Semantic Partitioning
- Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog
- HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions
- VeriRAG: A Retrieval-Augmented Framework for Automated RTL Testability Repair
- HWE-Bench: Benchmarking LLM Agents on Real-World Hardware Bug Repair Tasks
- SynthAI: A Multi Agent Generative AI Framework for Automated Modular HLS Design Generation
- Evaluating Large Language Models Trained on Code
- Rethinking Code Complexity Through the Lens of Large Language Models
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