BEHAVE: Functional Behavior Modeling Enables Self-Improving Agents for Hardware Design and Verification
cs.AI, cs.AR, cs.LG
Submitted: 2026-09-28
Updated: 2026-09-28
Code: https://github.com/joel-wu/BEHAVE
Terminology
Sources
- ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generation
- ChatModel: Automating Reference Model Design and Verification with LLMs
- Faver: Boosting LLM-based RTL Generation with Function Abstracted Verifiable Middleware
- AutoVeriFix+: High-Correctness RTL Generation via Trace-Aware Causal Fix and Semantic Redundancy Pruning
- PRO-V-R1: Reasoning Enhanced Programming Agent for RTL Verification
- DeepSeekMath: Pushing the Limits of Mathematical Reasoning in Open Language Models
- Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
- GoGoTB: Agentic RTL Verification with Specification-Grounded Coverage Closure
- Using LLMs to Facilitate Formal Verification of RTL
- LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines
- Exploring the Agentic Frontier of Verilog Code Generation
- Agentic Hardware Design as Repository-Level Code Evolution
- VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs
- SpecLoop: An Agentic RTL-to-Specification Framework with Formal Verification Feedback Loop
- LLM-FSM: Scaling Large Language Models for Finite-State Reasoning in RTL Code Generation
- RefEvo: Agentic Design with Co-Evolutionary Verification for Agile Reference Model Generation
- UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification
- Evidence-Driven LLM Agent for C-to-Synthesizable-C Conversion and Verification
- MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization
- Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement
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