A High Gain Preamplifier Board for Low Charge Semiconductor Detectors

A High Gain Preamplifier Board for Low Charge Semiconductor Detectors

Abstract: The paper presents a high-gain, low-noise preamplifier board designed for reading out low-charge semiconductor detectors—specifically Low-Gain Avalanche Detectors (LGADs) and three-dimensional (3D) silicon sensors—in high-energy physics applications. The circuit employs a three-stage architecture featuring a discrete SiGe:C bipolar junction transistor (BJT)-based transimpedance amplifier (TIA) front-end followed by two resistive feedback amplification stages using LTC6431 chips. This configuration achieves a charge gain of 115.27 mV·ns/fC with excellent linearity over an input range of 0.5 fC to 25 fC and a wide bandwidth spanning from 34.0 MHz to 594.3 MHz. Experimental evaluations coupled with LGAD detectors demonstrate a time resolution of 36.41 ps and an equivalent noise charge (ENC) of 0.18 fC at 20 °C. Furthermore, tests with conventional PIN sensors without a gain layer yield a timing resolution of 76.10 ps with an ENC of 0.10 fC, and tests with the 3D silicon detector yield 39.40 ps with an ENC of 0.09 fC, all measured under the same thermal condition. All configurations confirm the board’s capability in low-signal regimes, significantly outperforming previous reference designs. A six-channel variant of the board has also been developed to support position-sensitive measurements. These findings demonstrate the board’s suitability for laboratory-based 4D tracking detector characterisation, while simultaneously providing the groundwork for dedicated ASIC development.

Introduction: High-energy physics experiments at the LHC and its future upgrades demand sub-100 ps timing resolution, micron-level spatial resolution, exceptional radiation hardness, high detection efficiency, and long-term operational stability. The LGAD provides internal gain (typically 10–30) while maintaining excellent time resolution (40 ps). AC-LGAD can determine hit position through signal interpolation among neighboring electrodes, achieving spatial resolution at the level of 10 µm to 50 µm while maintaining excellent timing performance (30 ps). 3D silicon detectors embed electrodes directly into the silicon bulk, decoupling electrode distance from substrate thickness, offering high spatial position, high radiation tolerance, and fast signal response without relying on a gain layer. However, 3D detectors generate very small charge outputs, approximately several fC or even below 1 fC, placing extreme demands on front-end electronics. Their rapid rise times (potentially < 500 ps) require front-end amplifiers with exceptionally high bandwidth (1 GHz). Most existing designs are tailored to a single detector type, and even the most sensitive discrete solutions have yet to demonstrate reliable performance for charge outputs below 1 fC—a critical requirement for 3D detectors with small signal. This gap motivates the work.

Electronic Design: To simultaneously achieve higher bandwidth and gain, single-stage amplification alone cannot satisfy system requirements, so multiple amplification stages are implemented. The transimpedance amplifier (TIA) was chosen over the charge-sensitive amplifier (CSA) because it enables bandwidths extending into the GHz range and accurately reproduces the input pulse shape at the output, maintaining temporal fidelity without introducing signal distortion. The first stage uses a discrete SiGe:C NPN BJT (BFP840FESD) with a transition frequency of 85 GHz, enabling a transimpedance gain resistor of 1.3 kΩ. The second and third stages use LTC6431 chips with a power gain of 20.8 dB and 2 GHz of f−3dB. The design includes DC-blocking capacitors, power supply inductors, and precise optimization of capacitor and inductor values. For noise reduction, the LT3042 power regulator (RMS noise of 0.8 µV, PSRR of 79 dB) is used for the first-stage transistors, and ADM7171 regulators (RMS noise 5 µV) for subsequent stages. A compact shielding enclosure was designed to mitigate external environmental interference. A dedicated injection current channel with a 1 pF capacitor (C1) is implemented for calibration. The PCB layout is optimized for high signal integrity, avoiding signal reflections and interference coupling. A six-channel version was developed with identical circuit architecture, with minor modifications to the DC low-voltage power supply to accommodate higher supply current.

Test Results: Small-signal AC parameter tests used an arbitrary waveform generator (WX2182C) to generate high-speed pulses (rise/fall time < 500 ps) injected through the calibration port, with a −40 dB attenuator to achieve minimum charge injection of 0.5 fC. The output was acquired with a LeCroy HDO9404 oscilloscope (4 GHz bandwidth, 40 GS/s sampling rate). The charge gain was measured as 115.27 mV·ns/fC over a charge range of 0.50 fC to 25 fC, with R2 of 0.9998 and maximum Integral Nonlinearity (INL) of 1.10%, showing good linearity. Frequency response analysis using a KEYSIGHT E5080B network analyzer showed a-3 dB bandwidth from 34.0 MHz to 594.3 MHz, intentionally constrained to prioritize adequate SNR over maximum bandwidth.

For β-scope tests, a USTC-fabricated sensor was bump-bonded to the electronics board and characterized using a 90Sr beta radiation source. The apparatus was housed in a temperature-controlled environmental chamber with electromagnetic shielding. A microchannel plate photomultiplier tube (MCP-PMT) served as the reference detector with 10 ps time resolution at −3000 V. The LGAD detector was biased at −165 V. Timing determination employed a 50% constant fraction discrimination (CFD) method. With the LGAD, the MPV of signal amplitude was 927.94 mV, RMS noise was 14.64 mV, SNR was 63.38, collected charge MPV was 11.66 fC, and ENC was 0.18 fC. The timing resolution improved from 38.25 ps (reference USTC-V1 board) to 36.41 ps. The electronic jitter was 10.9 ps for the new board versus 12.6 ps for the USTC-V1 board. The modest difference in timing resolution is attributed to the LGAD's high internal gain, where timing performance becomes less sensitive to moderate variations in front-end electronics gain and noise.

With a PIN diode (same process as USTC-IME LGAD wafer but without internal gain), the feedback resistor was adjusted to 1.13 kΩ to enhance gain. The MPV of pulse amplitude was 64.26 mV, RMS noise was 11.25 mV, SNR was 5.67, and ENC was 0.11 fC. The combined time resolution with the PIN detector was 76.10 ps, with electronic jitter of 42.9 ps. The USTC-V1 board coupled with the PIN detector exhibited poor SNR that precluded reliable discrimination between true signals and stochastic fluctuations, demonstrating it is inadequate for signal charges less than about 1 fC.

With a 3D silicon detector (pixel size 25 µm, ultra-thin active thickness 50 µm) at −70 V bias and 20 °C, the MPV of amplitude was 72.66 mV for a collected charge of 0.58 fC. The SNR was 6.46, ENC was 0.09 fC, and combined time resolution was 39.40 ps. A tail on the right side of the Gaussian peak was observed, attributed to non-uniform electric field distribution in the sensor. The electronic jitter was estimated at 31.1 ps, contributing substantially to time resolution due to the limited charge output from the 3D detector.

For the multi-channel board, charge gain measurements showed good inter-channel uniformity with a mean gain of 115.90 mV·ns/fC and standard deviation of 1.66 mV·ns/fC across six channels (individual gains: 116.74, 115.43, 113.51, 114.65, 117.86, 117.21 mV·ns/fC). Crosstalk tests involved injecting calibration signals into one channel while monitoring all others—no detectable signal was observed in non-injected channels. An optical validation test with a visible red laser aligned to the central pad of a 5×5 LGAD detector array showed a clear signal only in the corresponding central channel, with no measurable response in the five immediately surrounding channels, confirming no significant inter-channel crosstalk.

Conclusions: The preamplifier employs a TIA followed by two stages of resistive feedback gain amplification, enabling significant increase in overall voltage gain while maintaining adequate bandwidth. The multi-channel version provides the essential foundation for position-sensitive measurements. The board demonstrates a charge gain of 115.27 mV·ns/fC with excellent linearity over [0.5, 25] fC, and-3 dB bandwidth from 34.0 MHz to 594.3 MHz. All configurations—LGAD, PIN, and 3D silicon detectors—achieved favorable time resolution performance. The timing measurements with PIN and 3D detectors reveal that electronic jitter, primarily due to intrinsic noise, remains the dominant contribution when signals fall below 1 fC, identifying the need for either higher charge-yield sensors or more advanced fabrication technologies for further performance enhancement.

Improvements to AI Systems:

1. AI-Driven Front-End Electronics Co-Design Optimization: Train an AI system to automatically co-optimize preamplifier architectures (e.g., TIA vs. CSA, number of stages, transistor selection, feedback resistor/capacitor values) for given detector specifications (charge output, rise time, noise budget). The system would use the paper’s design constraints—SiGe:C BJT front-end, LTC6431 gain stages, bandwidth 34–594 MHz, charge gain 115.27 mV·ns/fC—as training data to predict optimal component values for new detector types (e.g., AC-LGAD, 3D sensors with <1 fC output), minimizing ENC and jitter while maximizing linearity.

2. Predictive Noise and Timing Resolution Modeling: Build a neural network or physics-informed ML model that takes detector parameters (internal gain, capacitance, rise time) and front-end characteristics (noise, bandwidth, jitter) to predict combined time resolution and ENC, as demonstrated in the paper (36.41 ps for LGAD, 76.10 ps for PIN, 39.40 ps for 3D). This AI system could rapidly evaluate design trade-offs without physical prototyping, enabling virtual screening of thousands of sensor-amplifier combinations for 4D tracking detectors.

3. Autonomous Calibration and Signal Discrimination for Low-Charge Regimes: Develop an AI-based readout system that uses the paper’s calibration injection method (1 pF capacitor, −40 dB attenuator) and CFD timing to automatically calibrate gain and threshold settings. For signals below 1 fC (as with PIN and 3D detectors), the AI could implement adaptive noise filtering, baseline correction, and pulse-shape recognition to improve SNR beyond the reported 5.67–6.46, potentially enabling reliable detection of sub-0.5 fC charges.

4. Multi-Channel Crosstalk and Position Reconstruction Enhancement: Use the six-channel board’s measured uniformity (mean gain 115.90 mV·ns/fC, σ=1.66) and crosstalk-free performance as a benchmark to train an AI algorithm for position-sensitive readout. The AI could interpolate signals across neighboring channels (as in AC-LGAD) to achieve sub-electrode spatial resolution (<25 µm), using the paper’s crosstalk validation data to ensure no false positives.

5. Design Rule Generation for ASIC Development: Extract the paper’s discrete-component design principles (TIA topology, resistive feedback, power regulation with LT3042/ADM7171, shielding) to train a generative AI that produces ASIC-level circuit schematics and layout guidelines. The AI would output optimized transistor sizing, biasing, and parasitic-aware routing rules for a dedicated readout chip, targeting the same performance metrics (115.27 mV·ns/fC gain, 0.18 fC ENC) but with lower power and smaller footprint.

6. Real-Time Detector Health and Performance Monitoring: Implement an AI system that continuously monitors the preamplifier’s output (gain, noise, jitter) across all channels, using the paper’s test methodology (frequency response, INL, SNR) as a baseline. The AI could detect degradation (e.g., radiation damage in sensors, component aging) by comparing live measurements to the paper’s reference values (e.g., ENC 0.09–0.18 fC, bandwidth 34–594 MHz) and trigger predictive maintenance or recalibration.

What the Improved AI System Can Do:

• Automatically design and validate front-end electronics for any low-charge semiconductor detector, reducing development time from months to hours.

• Predict timing resolution and noise for new sensor-amplifier combinations with <5% error, enabling rapid feasibility studies for future collider experiments.

• Enable reliable detection and timing of sub-femtocoulomb signals (down to 0.5 fC) with adaptive noise suppression, extending the board’s capability to ultra-thin 3D sensors.

• Provide sub-25 µm spatial resolution in multi-channel configurations by AI-based signal interpolation, surpassing the paper’s single-channel measurements.

• Generate ASIC-ready circuit designs with performance parity to the discrete board, accelerating the path to compact, radiation-hard readout chips.

• Operate as a self-calibrating, self-monitoring readout system for 4D tracking detectors, ensuring long-term stability in high-energy physics experiments.

We present a high-gain, low-noise preamplifier board designed for reading out low-charge semiconductor detectors--specifically Low-Gain Avalanche Detectors (LGADs) and three-dimensional (3D) silicon sensors--in high-energy physics applications. The circuit employs a three-stage architecture featuring a discrete SiGe:C bipolar junction transistor (BJT)-based transimpedance amplifier (TIA) front-end followed by two resistive feedback amplification stages using LTC6431 chips. This configuration achieves a charge gain of 115.27 mV ns/fC with excellent linearity over an input range of 0.5 fC to 25 fC and a wide bandwidth spanning from 34.0 MHz to 594.3 MHz. Experimental evaluations coupled with LGAD detectors demonstrate a time resolution of 36.41 ps and an equivalent noise charge (ENC) of 0.18 fC at 20 C. Furthermore, tests with conventional PIN sensors without a gain layer yield a timing resolution of 76.10 ps with an ENC of 0.10 fC, and tests with the 3D silicon detector yield 39.40 ps with an ENC of 0.09 fC, all measured under the same thermal condition. All configurations confirm the board's capability in low-signal regimes, significantly outperforming previous reference designs. A six-channel variant of the board has also been developed to support position-sensitive measurements. These findings demonstrate the board's suitability for laboratory-based 4D tracking detector characterisation, while simultaneously providing the groundwork for dedicated ASIC development.