FinHardBench: Can LLMs Generate Latency-Aware Hardware for Financial Computing?
Weimin Fu, Hejia Zhang, Minghao Shao, Zeng Wang, Johann Knechtel, Ozgur Sinanoglu, Muhammad Shafique, Ramesh Karri, Xiaolong Guo
cs.CL, cs.AR
Submitted: 2026-08-02
Comments: 16 pages (10 pages main text). Published as a conference paper at COLM 2026. Code and benchmark: https://github.com/owenfucell/FinHardBench
Code: https://github.com/owenfucell/FinHardBench
License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
Terminology
Sources
- ChipNeMo: Domain-Adapted LLMs for Chip Design
- Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
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