A Self-Calibrating Framework for Analog Circuit Sizing Using LLM-Derived Analytical Equations
cs.AR, cs.AI
Submitted: 2026-04-08
Updated: 2026-10-05
Comments: 14 pages, 4 figures, 7 tables, plus supplementary. V3: Extended to 8 topology families (6-30 transistors) across 6 process nodes with 5-trial statistics; adds cross-model evaluation (5 LLMs), ablation study, matched TuRBO-1 baseline, and structural audit of 2,634 LLM-derived equations
License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
Terminology
Sources
- AutoSizer: Automatic Sizing of Analog and Mixed-Signal Circuits via Large Language Model (LLM) Agents
- TopoSizing: An LLM-aided Framework of Topology-based Understanding and Sizing for AMS Circuits
- EasySize: Elastic Analog Circuit Sizing via LLM-Guided Heuristic Search
- AmpAgent: An LLM-based Multi-Agent System for Multi-stage Amplifier Schematic Design from Literature for Process and Performance Porting
Related papers
- WitCert: Sound Runtime Risk Observability and Gating for KV-Cache Quantization
- Golden Ruler: A Numeric Format Catalog with Bit-Exact Conformance Vectors for FP8, BF16, MXFP4, and Microscaling Formats
- RFChipAgent: Multi-Agentic AI Flow for Analog/RF Chip Design
- PoisonCap: Efficient Hierarchical Temporal Safety for CHERI
- Provisioning to Runtime Optimization of a 100 MW-Scale AI Cluster
- Bit-Accurate Modeling of GPU Matrix Multiply-Accumulate Units: Demystifying Numerical Discrepancy and Accuracy