Chiplet-Based RISC-V SoC with Modular AI Acceleration

arXiv:2509.18355 · cs.AR, cs.AI · Submitted 2025-09-22 · Read on arXiv

cs.AR, cs.AI

Submitted: 2025-09-22

Updated: 2026-10-17

Comments: 4 pages, 3 figures, 2 tables, 3rd IEEE International Conference of Computational Intelligence and Network Systems 2025

License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/

Terminology

• Edge AI — 2× in this paper · explained in 2 episodes
• Benchmark — 1× in this paper · explained in 2 episodes
• Energy Efficiency — 1× in this paper · explained in 3 episodes

Related papers

• WitCert: Sound Runtime Risk Observability and Gating for KV-Cache Quantization
• Golden Ruler: A Numeric Format Catalog with Bit-Exact Conformance Vectors for FP8, BF16, MXFP4, and Microscaling Formats
• RFChipAgent: Multi-Agentic AI Flow for Analog/RF Chip Design
• PoisonCap: Efficient Hierarchical Temporal Safety for CHERI
• Provisioning to Runtime Optimization of a 100 MW-Scale AI Cluster
• Bit-Accurate Modeling of GPU Matrix Multiply-Accumulate Units: Demystifying Numerical Discrepancy and Accuracy