Reducing the Computational Cost Scaling of Tensor Network Algorithms via Field-Programmable Gate Array Parallelism

Name: Reducing the Computational Cost Scaling of Tensor Network Algorithms via Field-Programmable Gate Array Parallelism
Uploaded: 2026-11-01T04:17:38.286044+00:00
Description: The work proposes a fine-grained parallel tensor network design using FPGAs to significantly improve computational efficiency for iTEBD and HOTRG algorithms. By employing a quad-tile partitioning strategy, the authors reduced computational cost scaling from O(Db^3) to O(Db) for iTEBD and from O(D^6b) to O(D^2b) for HOTRG, offering superior scalability over CPU/GPU implementations.

The work proposes a fine-grained parallel tensor network design using FPGAs to significantly improve computational efficiency for iTEBD and HOTRG algorithms. By employing a quad-tile partitioning strategy, the authors reduced computational cost scaling from O(Db^3) to O(Db) for iTEBD and from O(D^6b) to O(D^2b) for HOTRG, offering superior scalability over CPU/GPU implementations.

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