CascadeLUT: Information-Ordered Streaming Inference for Bandwidth-Constrained FPGAs
CascadeLUT is an inference framework designed for FPGAs with limited bandwidth by organizing neural networks into a statically scheduled cascade. It achieves 4x to 12x lower latency and 3x to 5x higher throughput than previous methods. The core innovation is ordering input features based on their importance (salience) rather than just arrival order, ensuring the most critical data influences computation earliest.