Resist-free shadow deposition using silicon trenches for Josephson junctions in superconducting qubits

Introduction to the show: ident: Quantum Radio. Generated commentary on the latest quantum physics and condensed matter papers.

Kai: We're looking at the paper: "Resist-free shadow deposition using silicon trenches for Josephson junctions in superconducting qubits".

Mira: Here's the gist of the paper. The gist The method demonstrates a resist-free approach to junction fabrication based on etched silicon trenches that is CMOS compatible and easily integrated into existing innovations in qubit base layer fabrication and chemical processing.

Kai: Problem Addressed Resist-based Josephson junction (JJ) schemes have largely remained unchanged, causing chemical contamination and limiting options for surface preparation, junction materials, deposition methods, and other fabrication process windows The presence of the polymer mask results in chemical contamination and severely limits options for surface preparation, junction materials, deposition methods, and other fabrication process windows.

Mira: Other fully subtractive methods have been explored but are hindered by the substantially larger number of process steps which must be optimized to achieve sufficiently high quality factor devices to be competitive.

Kai: Fabrication Scheme The junction fabrication scheme is based on etching trenches into the Si substrate, where the sidewalls provide a necessary shadowed area for an overlap region to form the junction while leaving non-overlapped regions for the two electrodes to climb the sidewall onto the top of the substrate.

Title and authors: Kai: Moving into the specifics of "Resist-free shadow deposition using silicon trenches for Josephson junctions in superconducting qubits," we're looking at how they physically set up this new fabrication route.

Mira: This paper is focused on replacing the old resist mask with etched silicon trenches to create the overlap region needed for a Josephson junction without any subtractive processing steps after deposition.

Lev: The core of their fabrication scheme is etching a trench into a high-resistivity silicon substrate, where the sidewalls are crucial because they provide that necessary shadowed area for the overlap region to form while leaving non-overlapped regions for the two electrodes to climb onto the top of the substrate.

Kai: To achieve this, they use an HBr/Ar etch designed to maintain a smooth silicon surface throughout that trench etching process.

Mira: After defining that structure, they thermally oxidize the substrate to grow SiO2 for a hard mask, and then define an etch mask with electron-beam lithography followed by a CHF3/O2-based dry-etch process.

Lev: They then etch the silicon using that SiO2 hard mask with another HBr/Ar etch to achieve a silicon trench depth of approximately one point one µm and a sidewall angle of approximately eighty five to eighty eight degrees <ref:2604.09796#pg1>.

Kai: A key part is stripping that hard mask off using ten to one hydrofluoric acid, and then soaking the chip in ten to one buffered oxide etch or BOE to strip any native silicon dioxide and remaining resist residue.

Mira: After cleaning everything up, they move on to the deposition phase, where they evaporate the aluminum electrodes at forty nine degrees Celsius at a rate of two angstrom per second.

Lev: They make sure the bottom electrode is deposited first and subsequently oxidized before depositing the top electrode.

Kai: The structure itself is controlled by modulating that trench width; specifically, "the overlap region is formed at the widest part of the trench, and narrower parts of the trench result in only single layers of aluminum elsewhere in the trench or on the sidewalls."

The paper's summary: Mira: So to summarize what they did is that they demonstrated a subtractive-free method for junction fabrication by using etched silicon trenches to control overlap region geometry.

Kai: They showed that by controlling the width of those trenches, you can precisely control the junction width and length, which directly controls how the overlap region forms.

Mira: This geometric control is key because it avoids traditional resist-based contamination issues and allows for a more direct integration into existing qubit base layer fabrication processes.

Lev: The summary emphasizes that this method eliminates the need for additional subtractive processing to form the junction, which is a big win if you're trying to keep the process steps down.

Kai: They also focused heavily on showing that their interface characterization confirmed high cleanliness at the atomic scale, finding no evidence of carbon contamination in the evaporated aluminum or any interfaces.

Mira: They quantified this cleanliness by showing an oxide layer thickness between one point six and one point nine nanometers and confirming crystalline aluminum grains in both electrodes with sizes ranging from ten to fifty nanometers for the bottom electrode.

Lev: The summary also includes that they are using a variable width trench to form the overlap region, which is shown in cross-sectional SEM images of a three micro meter wide trench with the evaporated layers and a clear overlap region.

The paper's improvements: Kai: One major improvement they point out is that this new approach offers an extensive exploration of the interplay between alternative materials with qubit performance without being limited by the damage seen in traditional trilayer junction fabrication schemes.

Mira: This material agnosticism means AI design tools can rapidly screen and optimize novel material combinations for Josephson junctions, which is a major step forward for finding better qubit performance.

Lev: For real hardware implementation, this translates to being able to predict how qubit coherence metrics like T1 and Q1 based on the physical dimensions of the trench and electrode overlap region during the design phase.

Kai: They also suggest that because of this clean interface, AI can monitor fabrication processes in real time, identifying any deviations that might cause carbon or oxygen buildup before it compromises qubit performance.

Mira: And their statistical analysis using long time traces and overlapping Allan deviation and spectral density lets AI automatically extract noise characteristics from experimental data to identify specific noise processes like Lorentzian components that indicate telegraph switching due to strongly coupled TLS.

Lev: Using the robust coefficient of variation as a metric is suggested because it shows lower fluctuations compared to recent works with comparable quality factors, allowing AI systems to prioritize device designs based on long-term stability rather than just peak performance.

Conclusion: Kai: So, wrapping up this discussion on "Resist-free shadow deposition using silicon trenches for Josephson junctions in superconducting qubits," the main implication is a substantial widening of the process window for junction fabrication.

Mira: They've shown that this scheme is material-agnostic and integrates well with current silicon qubit base layer fabrication processes, which could speed up exploration of new materials significantly.

Lev: For me, I just think that if they can get this level of control over the geometry reliably on a larger scale, it starts to make the overhead for running these qubits on real hardware more manageable.

Kai: It’s a proof-of-principle demonstration that we can produce high-quality qubits using this new technique, and it opens the door for exploring other electrode and tunnel barrier materials in the future.

Mira: We're seeing a robust coefficient of variation below zero point two, which is a strong indicator of lower long-term fluctuations compared to recent works with comparable quality factors.

Lev: I just think the next step needs to be moving beyond T1 and Q1 measurements and really looking at how this noise profile changes under more demanding error correction scenarios.

Kai: It’s a solid demonstration that a method built on etched silicon trenches can deliver high-quality junction fabrication for superconducting qubits.